FIG. 1 shows a typical clock generator system for a processing chip such as a multi-core server or smart phone chip. It includes a phase locked loop (PLL) 102, a clock distribution circuit 104, and a feedback divider (FB Divider) 106. The PLL generates a clock and provides it to the clock distribution circuit 104, controlling its output (Clk Out) so that its frequency and phase track an input reference (Ref) clock, albeit multiplied in accordance with the FB Divider ratio. That is, the Clk Out frequency will typically equal the Ref Clk frequency multiplied by the FB Divider value. So, for example, if the FB Divider 106 constitutes a Div/8 circuit, then the Clk Out frequency would be 8 times that of the Ref Clk.
The clock distribution circuit (sometimes referred to as a clock tree or the like) may include buffers and other digital and/or analog circuit blocks for distributing multiple outputs of the clock produced by the PLL. Depending upon the application, as well as on design considerations, the clock distribution circuit, in whole or in part, may or may not be on the same chip as the PLL.
In many cases, the PLL is started under strong bias conditions in order to achieve stable oscillation with reasonable lock times. The strong bias condition typically corresponds with an initial high frequency output. For example, the operational reference clock may be at 2 GHz, but the PLL might start at around 5 GHz. Unfortunately, since the initial PLL frequency is high, the distribution circuit 104 is typically over-designed to operate with such high frequencies. For example, the clock distribution circuit may require larger devices or higher supply levels for the clock distribution supply since the PIX will not lock if the supply voltage is below the point that can support the initial PLL high-frequency condition. The clock distribution loading may also cause spikes on the PLL if the voltage supply of the PIX is coupled to the voltage supply of the clock distribution. This can cause extended lock time and instability, e.g., should a resonance condition be introduced due to the supply droop and subsequent correction.
Accordingly, solutions to these and other problems may be desired.